TEST

This instruction performs a bitwise AND operation between the destination operand and the source operand (destination AND source). Neither of the operands is modified.

The flags are modified as follows:

• CF=0.
• If the result is zero, then ZF=1. Otherwise, ZF=0.
• If the most significant bit of the result is 1, then SF=1. Otherwise, SF=0.
• OF=0.

Usage

TEST dest, source

The valid combinations for dest and source are:

• Register, register
• Register, memory address
• Register, immediate
• Memory address, register
• Memory address, immediate

(See operand types)

Encoding

• REGISTER to register
  1010001w, 00RRRrrr
• Memory (direct) to register
  1010001w, 01000rrr, addr-low, addr-high
• Memory (indirect) to register
  1010001w, 01010rrr
• Memory (indirect with displacement) to register
  1010001w, 01100rrr, disp-low, disp-high
• Immediate to register
  1010001w, 01001rrr, data-low, data-high
• Register to memory (direct)
  1010001w, 11000rrr, addr-low, addr-high
• Register to memory (indirect)
  1010001w, 11010rrr
• Register to memory (indirect with displacement)
  1010001w, 11100rrr, disp-low, disp-high
• Immediate to memory (direct)
  1010001w, 11001000, addr-low, addr-high, data-low, data-high
• Immediate to memory (indirect)
  1010001w, 11011000, data-low, data-high
• Immediate to memory (indirect with displacement)
  1010001w, 11101000, disp-low, disp-high, data-low, data-high

Where w is the operand size bit. w=0 indicates 8-bit operands, and w=1 indicates 16-bit operands. When w=0, data-high is omitted (the instruction length is one byte shorter).

rrr or RRR encodes a register according to the following table:

rrr	w=0	w=1
000	AL	AX
001	CL	CX
010	DL	DX
011	BL	BX
100	AH	SP
101	CH	--
110	DH	--
111	BH	--